Cisco Nexus V9P-3 200Gigabit Ethernet Card

Highest-density network application card

The Cisco Nexus® SmartNIC+ V9P is an FPGA-based network application card, optimized for low latency and high density.

The device packs a powerful 16nm Xilinx Virtex UltraScale Plus (VU9P) FPGAs with 2.5M logic cells, into a compact, half-height, half-length, PCIe 16x form factor.

High-capacity and low-latency memory | An extensive memory hierarchy for complex, memory-intensive applications

The Xilinx VU9P FPGA (Field Programmable Gate Array) features 75Mbit of block RAM and 270Mbit of UltraRAM on chip. The Cisco Nexus SmartNIC+ V9P further incorporates an additional 9GB of DDR4 DRAM on the board for high throughput access. The DRAM is accessible via a 72-bit-wide bus for maximum performance.

The Cisco Nexus V9P-3 FPGA Application SmartNIC model performs at a higher speed reducing the compile time by 40% over the V9P model compile times, that reduces project build time while increasing network uptime. The improved V9P-3 model logic performance and the faster clocked FPGA helps to eliminate any timing issues and can be programmed to reduce network latency to create a better user experience.

High-bandwidth connectivity | Dual QSFP-DD ports provide up to 400Gbps of full duplex connectivity.

The dual QSFP-DD ports offer high-speed 4x40GbE or 2x200GbE connectivity. Using QSFP-DD breakout cables expands the connectivity to 16x10GbE/25GbE4 connections. This high-density connectivity enables a range of high-performance, directly connected network applications, bypassing the need for traditional switching and multiplexing requirements.

Extensive IP library | Cisco is a specialist in low-latency, high-performance FPGA IP cores.

We provide you the same high-speed, low-latency IP blocks used in our market leading products, including:

• 10GbE PCS/MAC with ultra-low-latency performance
• Low-latency, high-throughput PCIe DMA engine
• Timing, signaling, and register interfaces, including I2C
• Packet field extractor and frame multiplexer (with source code)
• Asynchronous FIFO and CDC modules (with source code)

Several example designs are also provided to help get design work started and completed quickly.

• 100GBase-SR4
• 40GBase-SR4
• 40GBAse-LR4
• 100GBase-LR4